The impact of electrical stress on the defect generation behaviors in thin GeO₂/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO₂/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence ( ${Q} _{{\text {inj}}}$ ), and the fix charge generation is attributed to both ${Q} _{{\text {inj}}}$ and GeO₂ thickness.

中文翻译：

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电应力对热氧化制备的薄 GeO2/Ge 栅极堆叠中缺陷产生的影响

通过测量瞬态介电击穿 (TDDB) 和应力引起的漏电流 (SILC) 特性，研究了电应力对薄 GeO ₂ /n-Ge 栅叠层中缺陷生成行为的影响。证实了多点击穿 (BD) 事件，以及与 SiO ₂ /Si 结构相比更大的 SILC 生成概率。发现慢陷阱的产生主要取决于注入的电子注量（ ${Q} _{{\text {inj}}}$ )，固定电荷的产生归因于两者 ${Q} _{{\text {inj}}}$ 和GeO ₂厚度。