The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current ( ${I}_{eff}$ ) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in total current driving capability ( ${I}_{eff}$ ). Therefore, to enable future devices, we explored electrostatics and effective drive current ( ${I}_{eff}$ ) in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced device simulator, TCAD Sentaurus.

中文翻译：

---

3 纳米节点及以上器件缩放的机会：FinFET 与 GAA-FET 与 UFET

FinFET、环栅 (GAA) 纳米线/纳米片和 U 形 FET (UFET) 的性能针对 3 纳米节点 (N3) 和 CMOS 尺寸以外的尺寸进行研究。为了适应 32 nm 及以下的接触栅节距 (CGP)，栅长缩小到 14 nm 及以上。当从 5 纳米节点 (N5) 到 3 纳米节点 (N3) 尺寸时，GAA 横向纳米片 (LNS) 显示有效漏极电流降低了 8%（ ${I}_{eff}$ ) 由于短沟道效应的大幅上升，例如亚阈值斜率 (SS) 和漏极引起的势垒降低 (DIBL)。另一方面，基于 5 纳米直径的横向纳米线的总电流驱动能力提高了 80%（ ${I}_{eff}$ ）。因此，为了实现未来的设备，我们探索了静电和有效驱动电流（ ${I}_{eff}$ ) 在按比例缩放的 FinFET、GAA-FET 和 UFET 架构中。使用先进的器件模拟器 TCAD Sentaurus 比较基于 Si 和 SiGe 的晶体管的性能。