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A 0.4 V, tail-less, fully differential trans-conductance amplifier: an all inverter-based structure
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2020-05-21 , DOI: 10.1007/s10470-020-01662-5
Hassan Faraji Baghtash

A tail-less, fully differential trans-conductance amplifier is presented in this paper. The proposed structure arranges the inverters as a core amplifier blocks in an elaborate manner to achieve fully differential function with tail-less power optimized elements. As the inverters are current push–pull structures, they reuse the bias current effectively to maximize the trans-conductance of block. The proposed amplifier structure exploits this to reduce the power consumption of proposed structure to 2.6 µW. Post-layout simulations with a load capacitance of 5 pF and power supply of 0.4 V have been performed to validate the performance of the proposed amplifier. The proposed amplifier exhibits a DC gain of 72.6 dB and a phase margin of 56° at unity-gain frequency of 327 kHz for a load of 5 pF. The proposed structure also delivers high common mode rejection ratio and power supply rejection ration values of 111 dB and 103 dB, respectively. To investigate the performance of the design over process and temperature variations, the Monte Carlo and corner simulations are performed, as well. The simulations are conducted with TSMC 180 nm CMOS technology file with Spectre simulation engine.



中文翻译:

0.4 V,无尾的全差分跨导放大器:全基于逆变器的结构

本文提出了一种无尾的全差分跨导放大器。所提出的结构将逆变器精心设计为核心放大器模块,以利用无尾功率优化元件实现完全差分功能。由于反相器是电流推挽结构,因此它们可以有效地重用偏置电流,以使模块的跨导最大化。拟议的放大器结构利用这一点将拟议结构的功耗降低到2.6 µW。已经执行了具有5 pF的负载电容和0.4 V的电源的布局后仿真,以验证所提出放大器的性能。拟议的放大器在5 pF的负载下,在327 kHz的单位增益频率下具有72.6 dB的DC增益和56°的相位裕度。所提出的结构还提供了高共模抑制比和111dB和103dB的电源抑制比值。为了研究设计在工艺和温度变化范围内的性能,还进行了蒙特卡洛和转角仿真。使用带有Spectre仿真引擎的TSMC 180 nm CMOS技术文件进行仿真。

更新日期:2020-05-21
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