This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were ±0.83/-0.54 and ±0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

中文翻译：

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具有比较器校准功能和反冲降噪功能的0.3V 10b 3MS / s SAR ADC，适用于生物医学应用。

本文介绍了一种10位逐次逼近式模数转换器（ADC），该器件以0.3V的超低电压工作，可应用于生物医学植入物。这项研究提出了几种改善ADC性能的技术。利用流水线比较器来保持动态比较器的优势并降低反冲噪声。重量偏置校准用于校正偏移电压，而不会降低比较器的工作速度。合并单位增益缓冲器改善了保持期间的自举开关泄漏问题，并减少了寄生电容对数模转换器的影响。该芯片是使用90纳米CMOS技术制造的。在电源电压为0时测量的数据。差分非线性和积分非线性的3 V和3 MSps采样率分别为±0.83 / -0.54和±0.84 / -0.89，信噪比和失真比以及有效位数为56.42 dB和9.08 b ， 分别。在4.065 fJ /转换步的品质因数下，测得的总功耗为6.6μW。