A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm2 and fabricated in 180-nm CMOS technology, achieves 22 e− equivalent noise charge (ENC) and a dynamic range of 190 ke− (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a $256\times256$ pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron.

中文翻译：

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用于具有 78.7-dB 动态范围的列并行 CCD 的 4 MHz、256 通道读出 ASIC

介绍了一种称为极低噪声模拟采样引擎 (VASE) 的 256 通道读出专用集成电路 (ASIC)，用于读出列平行电荷耦合器件 (CP-CCD)。每个通道都使用一个电荷敏感放大器和一个一阶双增益 Sigma-Delta 模数转换器 (ADC)，它们充当扩展计数 ADC 的前端。扩展计数 ADC 直接实现相关多重采样作为其操作的一部分。为了减少输入电容引起的噪声并确保紧凑的相机，VASE 输入焊盘与 CP-CCD 的间距匹配，以允许以最小寄生电容进行芯片到芯片的键合。该芯片采用模块化设计，每 16 个输入通道共享一个差分模拟输出和数字串行器。VASE，芯片面积为 38。1 mm2 并采用 180-nm CMOS 技术制造，在 4-MHz 像素速率（对应于 32 kfps 的帧速率）下实现 22 e− 等效噪声电荷 (ENC) 和 190 ke− (78.7 dB) 的动态范围一个 256 美元\times256 美元的像素传感器在两侧读出），同时每通道耗散 10.1 mW。该原型已用于在软 X 射线同步加速器上成功地对 X 射线衍射成像。