This paper presents a new optimized design to implement Fast Fourier Transform in orthogonal frequency division multiplexing for real valued signals. The proposed method is a new pipelined design, it is the combination of serial as well as parallel split and merge processing butterfly units. The proposed design initially has a single processing unit, in second stage, processing unit splits into two parallel processing units, and thereafter from stage three onwards, merges into a single processing until the last stage. The proposed design is optimized to reduce the latency as well as the hardware complexity for real inputs and complex inputs, as real valued signals itself reduce half of the computations, redundant data paths are eliminated effectively by this design. The parallel processing unit speeds up the processing at the initial stage, whereas single processing units reduce the hardware complexity. This design is a solution for ambiguity between Latency and hardware. The proposed design is very effective for real valued signals. The proposed design is implemented in Radix-2² model, in which multipliers are required for every two stages. The proposed design reduces Latency parameter more than 50% with a small cost of adders and multipliers, also power consumption for higher order FFT’s is low.

本文提出了一种新的优化设计，可以在实频信号的正交频分复用中实现快速傅立叶变换。所提出的方法是一种新的流水线设计，它是串行，并行拆分和合并处理蝶形单元的组合。所提出的设计最初具有单个处理单元，在第二阶段，将处理单元分为两个并行处理单元，然后从第三阶段开始，合并为单个处理，直到最后一个阶段。拟议的设计经过优化，可减少实际输入和复杂输入的等待时间以及硬件复杂性，因为实际值信号本身减少了一半的计算，因此该设计有效地消除了冗余数据路径。并行处理单元可以在初始阶段加快处理速度，而单个处理单元降低了硬件复杂性。此设计是解决延迟和硬件之间歧义的方法。所提出的设计对于实值信号非常有效。建议的设计在Radix-2中实现^2个模型，其中每两个阶段都需要乘数。所提出的设计以较小的加法器和乘法器成本将延迟参数降低了50％以上，而且高阶FFT的功耗也很低。