In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs.

中文翻译：

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技术对基于CNTFET的电路性能的影响

在本文中，我们对技术对基于CNTFET的电路性能的影响进行了研究。特别是，我们展示了一个非门的布局，它用作构建非门和环形振荡器链的模块。然后，我们介绍这些电路的时域仿真，以了解寄生元件如何限制CNTFET的高速性能。