A method is proposed for probabilistic testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities with the goal of assessment of pseudorandom test quality in digital circuits. The structure of the circuit is modeled as a macro-level network, where macros denote Fan-out-Free Regions (FFRs) of the circuit, which are represented as Structurally Synthesized BDDs (SSBDDs). SSBDD based representation allows signal probability calculation with higher speed and accuracy than using gate-level calculation approach. The proposed method is based on tracing true paths in SSBDDs, which avoids errors caused by signals' correlation and possible redundancy in the circuit, that is not possible in gate-by-gate probability calculation. A method is proposed for proving redundancy of faults, which is an extension of the same idea of SSBDD path tracing used for probability calculation. Experimental results show higher accuracy and considerable speed-up of probabilistic analysis using the proposed new macro-level approach, compared to gate-level calculation.

提出了一种数字电路的概率可测性分析方法，重点是根据信号概率来计算概率可控性指标，以评估数字电路的伪随机测试质量为目标。电路的结构被建模为宏级网络，其中宏表示电路的无扇出区域（FFR），它们表示为结构综合BDD（SSBDD）。与基于门级的计算方法相比，基于SSBDD的表示方法可以更快，更准确地计算信号概率。所提出的方法基于在SSBDD中跟踪真实路径，避免了信号相关性和电路中可能存在的冗余所导致的错误，这在逐个门的概率计算中是不可能的。提出了一种用于证明故障冗余的方法，该方法是用于概率计算的SSBDD路径跟踪的相同思想的扩展。实验结果表明，与门级计算相比，使用所提出的新的宏级方法可以提高概率分析的准确性和速度。