This work presents a Cap-less Low-Drop Out (LDO) Voltage Regulator that uses a Bootstrap Flipped-Voltage Follower (B-FVF) as the input stage of its active compensation network. Previous works use active compensation networks whose frequency response shows a high-pass behavior that depends on their compensation capacitor C_f. The dominant pole is related to the value of C_f. By using the B-FVF, this C_f-pole dependency is broken; only the gain of the compensation loop lies on C_f, while the high-pass pole is referred to the B-FVF input node capacitance. This advantage allows the integration of a smaller C_f, a 10X reduction compared with the state-of-the-art, and easier placement of the high-pass pole to higher frequencies than the LDO open-loop Gain Bandwidth (GBW). The proposed LDO presents a quiescent current consumption of 95 μA at a 1.8 V input voltage, delivering a 0mA–50mA load current at a 1.6 V output voltage. A load and line transient responses of 133 mV and 165 mV were measured by using a C_f of only 0.3 pF and a load capacitor C_L of 100 pF. In order to validate the proposed LDO, simulations and measurements were performed in 0.18 μm CMOS Standard technology. The silicon area consumption is 0.133 mm².

这项工作提出了一种无帽低压降（LDO）稳压器，该稳压器使用自举翻转电压跟随器（B-FVF）作为其有源补偿网络的输入级。先前的工作使用有源补偿网络，该有源补偿网络的频率响应显示出取决于其补偿电容器C _f的高通行为。主导极点与C _f的值有关。通过使用B-FVF，此C _f极相关性被打破；只有补偿环路的增益位于C _f上，而高通极点称为B-FVF输入节点的电容。这一优势允许集成更小的C _f，与最新技术相比降低了10倍，并且比LDO开环增益带宽（GBW）更容易将高通极放置于更高的频率。拟议的LDO在1.8 V输入电压下的静态电流消耗为95μA，在1.6 V输出电压下提供0mA–50mA的负载电流。通过仅使用0.3 pF的C _f和100 pF的负载电容器C _L可以测得133 mV和165 mV的负载和线路瞬态响应。为了验证所提出的LDO，在0.18μmCMOS标准技术中进行了仿真和测量。硅面积消耗为0.133mm ²。