A wideband bipolar low‐noise amplifier (LNA) with enhanced linearity operating in 0.5 to 6 GHz frequency range is proposed in this letter. The LNA design is based on a cascode amplifier with an emitter degeneration RC parallel network and a resistive shunt‐shunt feedback which can improve linearity. The cascode topology in conjunction with the preceding series inductor L is utilized to achieve good wideband input impedance matching, while the wideband output impedance matching is realized by using an emitter follower as a buffer. And the third‐order input intercept point (IIP3) has been improved due to the derivative superposition technique. The wideband LNA presented in this letter was designed and implemented in a JAZZ 0.18 μm SiGe BiCMOS process. The measured results show that from 500 MHz to 6 GHz, the power gain (S₂₁) is 16.5 to 17.1 dB, the noise factor (NF) is 2.7 to 3.3 dB, the current consumption without buffer stage is 12.4 mA at a 3.3 V supply voltage, and the IIP3 is −0.834 dBm at 2 GHz. The chip size is 1.06 × 0.64 mm².

中文翻译：

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0.5至6 GHz宽带共源共栅LNA，采用电阻分流-反馈和微分叠加，具有增强的线性度

本文提出了一种在0.5至6 GHz频率范围内具有增强线性度的宽带双极低噪声放大器（LNA）。LNA设计基于具有发射极退化RC并联网络和可改善线性度的电阻式并联反馈的共源共栅放大器。共源共栅拓扑结构与前面的串联电感器L结合使用可实现良好的宽带输入阻抗匹配，而宽带输出阻抗匹配则通过使用发射极跟随器作为缓冲器来实现。由于微分叠加技术，三阶输入截取点（IIP3）得到了改进。本文中介绍的宽带LNA是在JAZZ 0.18μmSiGe BiCMOS工艺中设计和实现的。测量结果表明，从500 MHz到6 GHz，功率增益（S₂₁）为16.5至17.1 dB，噪声系数（NF）为2.7至3.3 dB，在3.3 V电源电压下，不带缓冲级的电流消耗为12.4 mA，而IIP3在2 GHz下为-0.834 dBm。芯片尺寸为1.06×0.64 mm ²。