In this paper, a new design of low power, high performance Radix-4 MBW multiplier unit has been described. The low power performance has been achieved by dynamic voltage scaling. Based on CCGDI technique which reduces the switching activity and output capacitance, the proposed multiplier unit has been designed by utilizing three different low power methodologies i.e., reduction in output capacitance and switching activity along with biasing voltage reduction. In order to reduce the number of transistor and delay, here GDI based parallel adders are used in the Wallace tree counters. The multiplier has been implemented with constant threshold voltage PTM 45 nm devices technology and simulated in standard CAD tool simulator for 4, 8 and 16 bit operand multiplications. The proposed design consumes 238.98 µw average power and it has a propagation delay of 2.458 ns for 16 × 16 bit multiplications at speed 100 MBps which is 47% better in terms of power-delay-product than counter based GDI Wallace tree multiplier structure.

本文介绍了一种低功耗，高性能Radix-4 MBW乘法器单元的新设计。低功耗性能已通过动态电压缩放实现。基于减少开关活动和输出电容的CCGDI技术，通过利用三种不同的低功耗方法来设计所提出的乘法器单元，即降低输出电容和减少开关活动以及降低偏置电压。为了减少晶体管的数量和延迟，在Wallace树计数器中使用了基于GDI的并行加法器。该乘数已使用恒定阈值电压PTM 45 nm器件技术实现，并在标准CAD工具模拟器中进行了4、8和16位操作数乘法的模拟。提议的设计消耗238。