An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An (\(n+1\)) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to \(25.0\%\) in gate cost and \(35.8\%\) in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.

在测试，硬件和电子电路的速度之间需要进行激烈的权衡。通过利用Toffoli和Fredkin门的特性，本文提出了一种可测试性方法的有效设计，用于检测可逆电路中的卡住故障。找到了本文中描述的（\（n + 1 \））维通用测试集，可用于检测修改后的电路中的单个和多个固定故障。进行了一组基准电路进行实验，与证明该区域的现有工作相比，拟议工作的栅极成本降低了\（25.0 \％\），量子成本降低了\（35.8 \％\）它对降低硬件成本和降低速度造成的影响。