In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P⁺ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.

中文翻译：

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使用深沟道隔离的2D智能功率IC寄生抑制：仿真研究

在这封信中，提出了一种使用深沟槽隔离（DTI）技术的平面集成，以抑制以0.35 µm BiCMOS技术实现的智能功率集成电路中的阱间寄生虫。在这项技术中，所有器件都共享相同的外延层。这会导致功率器件之间以及功率和低压CMOS器件之间的穿通。DTI方案用于通过使用P ⁺来抑制寄生BJT的影响在深沟槽隔离区下方的延迟注入区。寄生BJT的注入率降低了3到8.5之间。使用SENTAURUS TCAD仿真研究了沟槽长度和延迟注入的影响。通过使用TCAD仿真，可以确认，敏感器件收集到的载流子数量随沟槽长度和延迟注入的存在而变化。