Real-time embedded systems need software and hardware to be time-predictable to guarantee the correct behavior of the system. Precision Timed Machines are architectures designed for timing predictability and repeatability. They help to improve design time and the efficiency of real-time embedded systems by allowing to separately verify the timing properties of modules. This paper presents a Simultaneous Multithreading Precision Timed Machine named Hivek-RT that can execute hard real-time and conventional threads in parallel. It employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy composed of scratchpads, caches, and a predictable SDRAM memory controller. The proposed architecture is well suited for real-time embedded systems as experimentation results show that the proposed architecture has improved throughput, presents low memory footprint and achieve a memory bandwidth of 90% of the theoretical value while providing deterministic time access to the memory hierarchy. This paper is an extended version of the paper presented on the 8th Brazilian Symposium on Computing Systems Engineering.

中文翻译：

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具有可预测时序行为的同时多线程处理器体系结构

实时嵌入式系统需要可预测时间的软件和硬件，以保证系统的正确行为。精密定时机是为定时可预测性和可重复性而设计的体系结构。它们允许分别验证模块的时序属性，从而有助于提高设计时间和实时嵌入式系统的效率。本文介绍了一种名为Hivek-RT的同步多线程精确定时机器，该机器可以并行执行硬实时和传统线程。它采用可重复的线程交错流水线，并具有由暂存器，高速缓存和可预测的SDRAM内存控制器组成的暴露内存层次结构。实验结果表明，该架构具有更高的吞吐量，因此该架构非常适合实时嵌入式系统。提供了确定的时间访问内存层次结构的方法，从而实现了低内存占用，并实现了理论值的90％的内存带宽。本文是在第八届巴西计算机系统工程研讨会上发表的论文的扩展版本。