Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.

中文翻译：

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在混合分层内存中利用内存间和内存内的不对称性进行数据映射

现代计算系统正在采用由 DRAM 和非易失性存储器 (NVM) 组成的混合存储器，以结合两种存储器技术的最佳特性，实现低延迟、高可靠性和高密度。DRAM-NVM 混合内存的一个突出特点是其 NVM 访问延迟远高于 DRAM 访问延迟。我们称之为内存间不对称。我们观察到长位线上的寄生元件是 DRAM 和 NVM 中高延迟的主要来源，也是导致 NVM 中高压操作的重要因素，这会影响它们的可靠性。我们提出了一种架构更改，其中 DRAM 和 NVM 中的每条长位线都被隔离晶体管分成两段。可以以比另一段更低的延迟和工作电压访问一个段。通过引入层级，我们在每种内存类型中启用非均匀访问（我们称之为内存内不对称），从而导致 DRAM-NVM 混合内存中的性能和可靠性权衡。我们以三种方式扩展现有的 NVM-DRAM OS。首先，我们利用内存间和内存内的不对称性在 DRAM 和 NVM 的层之间分配和迁移内存页面。其次，我们通过预测程序中新引用的内存页面的访问强度并在其初始分配期间将其放置到匹配层来改进操作系统的页面分配决策。这最大限度地减少了程序执行期间的页面迁移，从而降低了性能开销。第三，我们提出了一种在同一内存的层之间迁移页面而不通过内存通道传输数据的解决方案，最大限度地减少通道占用并提高性能。我们的总体方法，