An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed scheme achieves 98.45% saving in switching energy and 75% saving in total capacitors area compared with the conventional switching scheme. Furthermore, the voltage variation on positive and negative sides of capacitive digital-to-analog converter (CDAC) is equal in magnitude and opposite in direction until the last bit cycle, therefore the dynamic common-mode voltage variation range of CDAC is only 0.5LSB. Employing the proposed switching scheme, a 10-bit 200-kS/s 0.6-V SAR ADC is designed in 40-nm CMOS technology. Post-layout simulation results indicate that a SNDR of 57.1 dB can be achieved with the Nyquist input at 200-kS/s. The figure-of-merit of the proposed ADC is 1.37fJ/conversion-step.

提出了一种具有低共模电压变化和简单电容器阵列的节能开关方案，用于逐次逼近寄存器（SAR）模数转换器（ADC）。所提出的方案采用简单的二进制加权电容器阵列而不进行电容器分裂，并且在前两个比较周期中不消耗任何开关能量。行为仿真表明，与传统的开关方案相比，该方案可节省98.45％的开关能量，并节省75％的电容器总面积。此外，直到最后一个比特周期，电容式数模转换器（CDAC）的正负电压变化幅度相等，方向相反，因此CDAC的动态共模电压变化范围仅为0.5LSB 。采用建议的转换方案，采用40nm CMOS技术设计的10位200kS / s 0.6V SAR ADC。布局后的仿真结果表明，以200-kS / s的奈奎斯特输入可以实现57.1 dB的SNDR。拟议ADC的品质因数为1.37fJ /转换步长。