One of the most important issues in deep nanoscale regime CMOS circuits is related to the time-dependent performance degradation caused by negative bias temperature instability (NBTI). The integration of online aging sensor is becoming attractive methodologies in monitoring performance degradation of circuit. The sensor can generate a warning signal, early warning of the occurrence of aging faults, to avoid unnecessary losses. To accurately capture the aging fault, a real-time aging sensor is proposed with mirror extraction setup and hold (SH) time method. The proposed aging sensor, which is on the basis of the standard flip-flop (FF), consists of an additional edge detector circuit, a detection window generator circuit, and an output warning circuit. Having the adaptive characteristic of detection window, aging sensor is able to adjust its NBTI effects and improve the stability. Also, the sensing network supports multiple paths online detection from many SH sensors for IP chip applications. Finally, the Camellia IP layout is inserted with 20 aging sensors and is implemented under 65-nm CMOS process. Experimental results demonstrate the effectiveness of area, power, and performance overheads. Compared with other state of the art, hardware efficiency is increased by 46%, and energy is decreased by about 37%.

中文翻译：

---

实时SH老化传感器的设计及在传感网络中的应用

深纳米级 CMOS 电路中最重要的问题之一与由负偏置温度不稳定性 (NBTI) 引起的时间相关性能下降有关。在线老化传感器的集成正在成为监测电路性能退化的有吸引力的方法。传感器可产生预警信号，对老化故障的发生进行预警，避免不必要的损失。为了准确捕获老化故障，提出了一种采用镜像提取建立和保持（SH）时间方法的实时老化传感器。所提出的老化传感器是在标准触发器（FF）的基础上，由一个附加的边沿检测器电路、一个检测窗口生成器电路和一个输出警告电路组成。具有检测窗口自适应特性，老化传感器能够调整其NBTI效果并提高稳定性。此外，传感网络支持来自多个 SH 传感器的多路径在线检测，用于 IP 芯片应用。最后，Camellia IP 布局插入了 20 个老化传感器，并在 65-nm CMOS 工艺下实现。实验结果证明了面积、功率和性能开销的有效性。与其他现有技术相比，硬件效率提高了46%，能耗降低了约37%。和性能开销。与其他现有技术相比，硬件效率提高了46%，能耗降低了约37%。和性能开销。与其他现有技术相比，硬件效率提高了46%，能耗降低了约37%。