A low noise frequency quadrupler for differential crystal oscillators (XOs) with an integerated jitter of 67 fs_rms is proposed in this paper. A digitally duty cycle correction loop with fast convergence time is proposed to decrease the periodic deterministic jitter of the quadrupled reference clock. A ring-based injection-locked clock multiplier (ILCM) is implemented to show the effectiveness of the reference quadrupler. The output clock of ILCM achieves an integrated jitter of 387 fs_rms at 2.8 GHz output frequency with a total multiplication factor of 56 and 6.2 mW consumed power from 1.2 V supply. The proposed design was implemented using 130-nm CMOS process.

本文提出了一种具有67 fs _rms整数抖动的差分晶体振荡器（XO）的低噪声频率四倍频器。提出了一种具有快速收敛时间的数字占空比校正环路，以减少四倍参考时钟的周期性确定性抖动。实现了基于环的注入锁定时钟乘法器（ILCM），以显示参考四倍频器的有效性。ILCM的输出时钟在2.8 GHz输出频率下实现了387 fs _rms的集成抖动，总乘数为56，1.2 V电源消耗的功率为6.2 mW。拟议的设计使用130 nm CMOS工艺实现。