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Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism
IEEE Transactions on Parallel and Distributed Systems ( IF 5.3 ) Pub Date : 2020-09-01 , DOI: 10.1109/tpds.2020.2987894
Congming Gao , Liang Shi , Kai Liu , Chun Jason Xue , Jun Yang , Youtao Zhang

Solid state drives (SSDs) are constructed with multiple level parallel organization, including channels, chips, dies, and planes. Among these parallel levels, plane level parallelism, which is the last level parallelism of SSDs, has the most strict restrictions. Only the same type of operations that access the same address in different planes can be processed in parallel. In order to maximize the access performance, several previous works have been proposed to exploit the plane level parallelism for host accesses and internal operations of SSDs. However, our preliminary studies show that the plane level parallelism is far from well utilized and should be further improved. The reason is that the strict restrictions of plane level parallelism are hard to be satisfied. In this article, a from plane to die parallel optimization framework is proposed to exploit the plane level parallelism through smartly satisfying the strict restrictions all the time. In order to achieve the objective, there are at least two challenges. First, due to that host access patterns are always complex, receiving multiple same-type requests to different planes at the same time is uncommon. Second, there are many internal activities, such as garbage collection (GC), which may destroy the restrictions. In order to solve above challenges, two schemes are proposed in the SSD controller: First, a die level write construction scheme is designed to make sure there are always $N$N pages of data written by each write operation. Second, in a further step, a die level GC scheme is proposed to activate GC in the unit of all planes in the same die. Combing the die level write and die level GC, write accesses from both host write operations and GC induced valid page movements can be processed in parallel at all time. To further improve the performance of SSDs, host write operations blocked by GCs are suggested to be processed in parallel with GC induced valid page movements, bringing lesser waiting time cost of host write operations. As a result, the GC cost and average write latency can be significantly reduced. Experiment results show that the proposed framework is able to significantly improve the write performance without read performance impact.

中文翻译:

充分利用平面级并行提升SSD性能

固态硬盘 (SSD) 由多级并行组织构成,包括通道、芯片、管芯和平面。在这些并行级别中,平面级并行,即SSD的最后一级并行,限制最为严格。只有在不同平面访问相同地址的相同类型的操作才能并行处理。为了最大限度地提高访问性能,已经提出了一些先前的工作来利用平面级并行性来进行主机访问和 SSD 的内部操作。然而,我们的初步研究表明,平面级并行性还没有得到很好的利用,应该进一步改进。原因是平面水平平行度的严格限制难以满足。在本文中,提出了一种从平面到芯片的并行优化框架,通过巧妙地始终满足严格的限制来利用平面级并行性。为了实现这一目标,至少有两个挑战。首先,由于主机访问模式总是很复杂,同时接收到不同平面的多个相同类型的请求并不常见。其次,有很多内部活动,例如垃圾收集(GC),可能会破坏限制。为了解决上述挑战,SSD控制器提出了两种方案:首先,设计die级写构造方案,确保每次写操作总是有$N$N页的数据写入。其次,在进一步的步骤中,提出了die level GC方案,以在同一die的所有平面为单位激活GC。结合芯片级写入和芯片级 GC,可以始终并行处理来自主机写入操作和 GC 引起的有效页面移动的写入访问。为了进一步提高SSD的性能,建议将GC阻塞的主机写操作与GC引起的有效页面移动并行处理,从而减少主机写操作的等待时间成本。因此,可以显着降低 GC 成本和平均写入延迟。实验结果表明,所提出的框架能够在不影响读取性能的情况下显着提高写入性能。建议 GC 阻塞的主机写操作与 GC 引起的有效页面移动并行处理,从而减少主机写操作的等待时间成本。因此,可以显着降低 GC 成本和平均写入延迟。实验结果表明,所提出的框架能够在不影响读取性能的情况下显着提高写入性能。建议 GC 阻塞的主机写操作与 GC 引起的有效页面移动并行处理,从而减少主机写操作的等待时间成本。因此,可以显着降低 GC 成本和平均写入延迟。实验结果表明,所提出的框架能够在不影响读取性能的情况下显着提高写入性能。
更新日期:2020-09-01
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