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Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
IEEE Transactions on Nanotechnology ( IF 2.4 ) Pub Date : 2020-01-01 , DOI: 10.1109/tnano.2020.2981394
Chuan-Hui Shen , Wei-Yen Chen , Shen-Yang Lee , Po-Yi Kuo , Tien-Sheng Chao

In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, the crystallinity of poly-Si channels can be modified easily by changing the thickness of nitride layer. The better crystallinity of the devices with 60 nm top nitride is attributed to larger average grain size and fewer defects, leading to higher field-effect carrier mobility compared to 40 and 80 nm top nitride layer devices. Both n-type and p-type devices exhibit superior electrical characteristics including higher on-state current of 40 μA/μm (n-type) and 26 μA/μm (p-type), steep subthreshold swing of 82 mV/dec. (n-type) and 104 mV/dec. (p-type), an extremely low drain-induced barrier lowering (DIBL) of 4.6 mV/V (n-type) and 16.6 mV/V (p-type), and high Ion/Ioff current ratio larger than seven orders of magnitude. The thermal stability and gate stress reliability measurement of sidewall damascene GAA nanowire poly-Si devices were also investigated. With better crystallinity, electrical characteristics of GAA nanowire poly-Si devices degrade less under same elevated temperature condition. Devices characteristics remain unchanged after long gate stress time. This simple fabrication process makes it a potential candidate for future three-dimensional integrated-circuit (3D-IC) and low-cost Internet of Things (IoTs) applications.

中文翻译:

氮化物引起的应力影响侧壁镶嵌栅全环绕纳米线多晶硅 FET 的结晶度

在本文中,成功演示了使用侧壁镶嵌方法的多晶硅环栅 (GAA) 场效应晶体管 (FET)。通过控制氮化物层施加的应力,可以通过改变氮化物层的厚度轻松改变多晶硅沟道的结晶度。具有 60 nm 顶部氮化物层的器件具有更好的结晶度,这归因于更大的平均晶粒尺寸和更少的缺陷,与 40 和 80 nm 顶部氮化物层器件相比,导致更高的场效应载流子迁移率。n 型和 p 型器件都表现出优异的电气特性,包括 40 μA/μm(n 型)和 26 μA/μm(p 型)的更高导通电流,82 mV/dec 的陡峭亚阈值摆幅。(n 型)和 104 mV/dec。(p 型),4.6 mV/V(n 型)和 16.6 mV/V(p 型)的极低漏极诱导势垒降低(DIBL),以及大于七个数量级的高 Ion/Ioff 电流比。还研究了侧壁镶嵌 GAA 纳米线多晶硅器件的热稳定性和栅极应力可靠性测量。具有更好的结晶度,GAA 纳米线多晶硅器件的电气特性在相同的高温条件下降低得更少。经过长时间的栅极应力时间后,器件特性保持不变。这种简单的制造工艺使其成为未来三维集成电路 (3D-IC) 和低成本物联网 (IoT) 应用的潜在候选者。在相同的高温条件下,GAA 纳米线多晶硅器件的电气特性退化较少。经过长时间的栅极应力时间后,器件特性保持不变。这种简单的制造工艺使其成为未来三维集成电路 (3D-IC) 和低成本物联网 (IoT) 应用的潜在候选者。在相同的高温条件下,GAA 纳米线多晶硅器件的电气特性退化较少。经过长时间的栅极应力时间后,器件特性保持不变。这种简单的制造工艺使其成为未来三维集成电路 (3D-IC) 和低成本物联网 (IoT) 应用的潜在候选者。
更新日期:2020-01-01
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