In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. The process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions is especially prone to defects due to the complexity of the process, thus giving a very narrow processing window to achieve the desired device, yield and reliability results. In this paper we evaluate a critical defect of “Abnormal epi” seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die. These defects, depending on where in the layout they occur, can lead to catastrophic failure under higher test voltages due to the physical shorting of n and p FET devices. We also explore the process parameters which influence this defect including incoming surface conditions and propose mechanisms that lead to the defect. Further, an optimization of the processing parameters in the integration scheme to minimize the occurrence of these defects leads to yield gain and cost savings required for high volume manufacturing.

中文翻译：

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FinFET 中的异常硅锗 (SiGe) 外延生长

在先进的互补金属氧化物半导体 (CMOS) 技术节点中，微小的纳米级缺陷往往会对最终产品的良率和可靠性产生重大影响。随着鳍式场效应晶体管 (FinFET) 技术的进步，控制缺陷程度同时确保所需的工艺参数到位变得越来越具有挑战性。在源/漏 (S/D) 区选择性外延生长硅锗 (SiGe) 的工艺由于工艺的复杂性而特别容易出现缺陷，从而提供了一个非常窄的工艺窗口来实现所需的器件、良率和可靠性结果。在本文中，我们评估了在 FinFET 上原位硼 (B) 掺杂的 SiGe 选择性外延生长过程中出现的“异常外延”的关键缺陷。这里的异常外延是指在晶片管芯上随机出现的异常大且虚假的外延生长缺陷。由于 n 和 p FET 器件的物理短路，这些缺陷（取决于它们出现在布局中的位置）可能在更高的测试电压下导致灾难性的故障。我们还探索了影响该缺陷的工艺参数，包括传入的表面条件，并提出了导致缺陷的机制。此外，优化集成方案中的工艺参数以最大程度地减少这些缺陷的发生会导致大批量制造所需的产量增加和成本节约。由于 n 和 p FET 器件的物理短路，在更高的测试电压下可能会导致灾难性的故障。我们还探索了影响该缺陷的工艺参数，包括传入的表面条件，并提出了导致缺陷的机制。此外，优化集成方案中的工艺参数以最大程度地减少这些缺陷的发生会导致大批量制造所需的产量增加和成本节约。由于 n 和 p FET 器件的物理短路，在更高的测试电压下可能会导致灾难性的故障。我们还探索了影响该缺陷的工艺参数，包括传入的表面条件，并提出了导致缺陷的机制。此外，优化集成方案中的工艺参数以最大程度地减少这些缺陷的发生会导致大批量制造所需的产量增加和成本节约。