Step-FinFET is an improvisation in various electrical characteristics with a modified mechanism. The gate length 20 nm, 15 nm, 20 nm has allowed an acceptable driving current and considerable power consumption which longer the battery life. The study consist of electron density, electron velocity, mobility, electric field, and surface potential to relate the improved device performance. The major variation of drain current due to stress effect, tunneling, saturation factor, and minority factor has been investigated. This paper analyzes the parameters like transconductance (Gm), Drain conductance (gd), input capacitance (Cgg), cut off frequency (fT), power consumption, etc., for verifying the RF and analog application. Various short channel effect (SCE) also studied in terms of threshold voltage (Vth), sub-threshold swing (SS), drain induced barrier lowering (DIBL) and On/Off ratio are investigated with different gate length and drain bias. As a result the minimum values of threshold voltage, SS and DIBL calculated for gate length of 15 nm are 0.2426 V, 69 mV/dec, 14.6 mV/V, respectively.

Step-FinFET通过改进的机制即兴发挥了各种电气特性。栅极长度20 nm，15 nm，20 nm允许了可接受的驱动电流和相当大的功耗，从而延长了电池寿命。该研究包括电子密度，电子速度，迁移率，电场和表面电势，以关系改进的器件性能。研究了由于应力效应，隧穿，饱和因子和少数因子引起的漏极电流的主要变化。本文分析了跨导（Gm），漏极电导（gd），输入电容（Cgg），截止频率（fT），功耗等参数，以验证RF和模拟应用。还根据阈值电压（Vth），亚阈值摆幅（SS），研究了不同栅极长度和漏极偏置条件下的漏极诱导势垒降低（DIBL）和开/关比。结果，针对15nm的栅极长度计算的阈值电压，SS和DIBL的最小值分别为0.2426V，69mV / dec，14.6mV / V。