The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple implementation outperforms all other implementations using only one power supply. It is equivalent to the best other implementation using three power supplies. The best quaternary adder using a 2-bit binary adder, the interface circuits between quaternary and binary levels are just overhead compared to the binary adder. This result shows that the quaternary approach for adders use more transistors, more chip area and more power dissipation than the corresponding binary ones.

中文翻译：

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四元加法器的最佳实现

由 2 位二进制加法器、四进制到二进制解码器和二进制到四进制编码器组成的四进制 1 位加法器的实现与最近几个四进制加法器的实现进行了比较。这种简单的实现优于仅使用一个电源的所有其他实现。它相当于使用三个电源的最佳其他实现。最好的四进制加法器使用 2 位二进制加法器，四进制和二进制级之间的接口电路与二进制加法器相比只是开销。该结果表明，加法器的四进制方法比相应的二进制方法使用更多的晶体管、更多的芯片面积和更多的功耗。