当前位置：
X-MOL 学术
›
Microelectron. Eng.
›
论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration
Microelectronic Engineering ( IF 2.3 ) Pub Date : 2020-05-01 , DOI: 10.1016/j.mee.2020.111336 M.-L. Pourteau , A. Gharbi , P. Brianceau , J.-A. Dallery , F. Laulagnet , G. Rademaker , R. Tiron , H.-J. Engelmann , J. von Borany , K.-H. Heinig , M. Rommel , L. Baier
Microelectronic Engineering ( IF 2.3 ) Pub Date : 2020-05-01 , DOI: 10.1016/j.mee.2020.111336 M.-L. Pourteau , A. Gharbi , P. Brianceau , J.-A. Dallery , F. Laulagnet , G. Rademaker , R. Tiron , H.-J. Engelmann , J. von Borany , K.-H. Heinig , M. Rommel , L. Baier
|
This article has been withdrawn at the request of the author(s) and published in Micro and Nano Engineering. The Publisher apologizes for any inconvenience this may cause. The full Elsevier Policy on Article Withdrawal can be found at https://www.elsevier.com/about/our-business/policies/article-withdrawal
中文翻译：
用于混合 SET/CMOS 集成的亚 20 nm 多层纳米柱图案化
本文已应作者要求撤回，发表于Micro and Nano Engineering。出版商对此可能造成的任何不便深表歉意。完整的 Elsevier 文章撤回政策可在 https://www.elsevier.com/about/our-business/policies/article-withdrawal 找到
更新日期：2020-05-01
中文翻译：
用于混合 SET/CMOS 集成的亚 20 nm 多层纳米柱图案化
本文已应作者要求撤回，发表于Micro and Nano Engineering。出版商对此可能造成的任何不便深表歉意。完整的 Elsevier 文章撤回政策可在 https://www.elsevier.com/about/our-business/policies/article-withdrawal 找到
京公网安备 11010802027423号