Static random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

中文翻译：

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低功耗高速10T静态随机存取存储单元的设计和统计分析

基于静态随机存取存储器（SRAM）的高速缓存是电子设备的重要组成部分。随着技术节点的减少，功率损耗和稳定性已成为主要问题。已经开发了几种SRAM单元来解决稳定性和功耗问题。但是，对于亚纳米技术而言，要在SRAM单元的所有参数之间实现平衡性能仍然是一个挑战。本文提出了一种新颖的SRAM单元，与用于45 nm互补金属氧化物半导体（CMOS）技术的常规单元相比，它的总电量，静态功耗，延迟和稳定性更高。与6T，N-control（NC），10T sub和10T相比，建议的10T电池的总功率成本分别降低了90.3％，85.84％，51.02％和90.9％。同样，与6T，NC，10T-sub和10T相比，拟议电池的静态功耗成本分别降低了55.17％，5.72％，‐ 41.6％和52.9％。与其他10T电池相比，该电池具有更好的稳定性，更少的延迟和相当的面积。最后，SRAM单元的蒙特卡洛（MC）仿真和工艺分析验证了所提出的10T单元的效率。