Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.

管道模数转换器（ADC）设计过程包括几个重新设计步骤，以实现最佳解决方案。因此，设计人员更喜欢为此目的使用自动化算法。本文提出了一种针对CAD工具的自动算法，其中考虑了流水线ADC的良率和功耗之间的权衡。这种自动化算法得益于多种自由度，包括系统级到晶体管级参数，这有助于CAD工具找到优化的解决方案。它使设计人员可以考虑产量和功耗之间的权衡来选择最佳方案。为了评估该算法的功能，设计并分析了一个10位流水线ADC。该ADC具有10位分辨率和6.3 mW功率，91％的良率，55.3 dB SNDR和58.8 dB SFDR，这些都与算法结果非常吻合。与类似的设计相比，它提供了具有竞争力的品质因数（FOM），证明了该算法在寻找最佳解决方案方面的能力。