Scan design is extensively exploited to test transition delay faults (TDF). Broadside test commonly referred as launch on capture and skewed load test is also commonly referred as launch-on-shift are two approaches to test TDF’s through scan design. However arbitrary test vector pair application is not supported by scan design because of architectural constraint of scan and this eventually limits the fault coverage for TDFs. Arbitrary test vector application is supported in enhanced scan design which alleviates the problem of poor fault coverage. Enhanced scan design has high area overhead and this problem can be further tackled through interchanging extra flip-flop by hold latch in enhanced scan. However hold signal required in enhanced scan design consists of hold latch is fast in nature. This signal is exactly equivalent of scan enable signal in skewed load test. Enhanced scan cell using one clock cycle slower hold signal is implemented in delay testable enhanced scan flip-flop (DTESFF) design. Partial enhanced scan method based on DTESFF design by using controllability measures for scan flip-flop identification is proposed for high transition delay test coverage in this work. Simulation results demonstrate the test coverage improvement for TDF in ISCAS 89 benchmark circuits.

中文翻译：

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在基于DTESFF的部分增强扫描设计中利用可控性措施实现高转换延迟测试覆盖率

扫描设计被广泛用于测试过渡延迟故障（TDF）。宽边测试通常称为“捕获时发射”，而偏载测试也通常称为“移位时发射”，这是通过扫描设计测试TDF的两种方法。但是，由于扫描的体系结构限制，扫描设计不支持任意测试向量对应用程序，这最终限制了TDF的故障范围。增强的扫描设计支持任意测试向量应用程序，从而减轻了错误覆盖范围的问题。增强型扫描设计具有较高的面积开销，可以通过在增强型扫描中通过保持锁存器交换额外的触发器来进一步解决此问题。但是，增强型扫描设计中由保持锁存器组成的保持信号本质上是快速的。该信号与偏载测试中的扫描使能信号完全等效。在延迟可测试的增强型扫描触发器（DTESFF）设计中实现了使用一个时钟周期慢速保持信号的增强型扫描单元。提出了一种基于DTESFF设计的局部可控扫描方法，该方法利用可控制性措施对扫描触发器进行识别，以实现高转换延迟测试覆盖率。仿真结果表明，在ISCAS 89基准电路中TDF的测试覆盖范围得到了改善。