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Energy Efficient Peripheral and System Buses for Low-Area and Low-Power SoC Applications
IEEE Transactions on Circuits and Systems II: Express Briefs ( IF 4.4 ) Pub Date : 2020-05-01 , DOI: 10.1109/tcsii.2020.2984018
Juan Romero , Nestor Cuevas , Elkim Roa

Nowadays, an SoC integrates a large number of modules within a single die, which requires implementing a robust communication system to link the whole chip. Buses are a convenient solution for connection of modules, arbitrating communication, timing, and transferring information along the SoC. Although the bus is an essential component in SoC applications, there is a lack of accurate literature about the topic. This brief spotlights the energy issues related to inefficient communication between a master and a time-constrained peripheral in standard bus approaches. Here we introduce an alternative bus protocol to allow direct communication among masters and slaves linked to the peripheral and system domains in low-energy applications. As a result of implementing the proposed bus within an SoC, we present a 5X clock cycle reduction for multiple transactions when compared to TileLink and AHB-Lite/APB approaches.

中文翻译:

用于小面积和低功耗 SoC 应用的节能外设和系统总线

如今,SoC 在单个芯片中集成了大量模块,这需要实现一个强大的通信系统来链接整个芯片。总线是用于连接模块、仲裁通信、时序和沿 SoC 传输信息的便捷解决方案。尽管总线是 SoC 应用中必不可少的组件,但缺乏有关该主题的准确文献。这篇简要介绍了与标准总线方法中主设备和时间受限外设之间低效通信相关的能源问题。在这里,我们引入了一种替代总线协议,以允许在低能耗应用中链接到外围设备和系统域的主设备和从设备之间进行直接通信。作为在 SoC 内实施建议的总线的结果,
更新日期:2020-05-01
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