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A High-Performance Design of Generalized Pipeline Cellular Array
IEEE Computer Architecture Letters ( IF 2.3 ) Pub Date : 2020-01-01 , DOI: 10.1109/lca.2020.2986197 Zhufei Chu , Huiming Tian , Zeqiang Li , Yinshui Xia , Lunyao Wang
IEEE Computer Architecture Letters ( IF 2.3 ) Pub Date : 2020-01-01 , DOI: 10.1109/lca.2020.2986197 Zhufei Chu , Huiming Tian , Zeqiang Li , Yinshui Xia , Lunyao Wang
In this letter, we proposed a high-performance quantum-dot cellular automata (QCA) design of generalized pipeline cellular array (GPCA). The GPCA can perform all the basic arithmetic operations using only one arithmetic cell. Due to its flexibility, the high-performance GPCA design is of high interest for large-scale QCA designs. We proposed both the arithmetic unit and control unit designs of GPCA using a hybrid logic network that represented by majority-of-three (MAJ), inverter (NOT), and three-input exclusive-OR (XOR$_3$ 3 ). The introduction of XOR$_3$ 3 operation can significantly reduce the number of gates, levels, and wire-crossings, which in turn results in less area and fewer clock cycles of QCA layout. Experiments show that we can achieve both area and latency improvements of $n$ n -bit (n = 3,4,5) GPCA designs compared with the-state-of-art.
中文翻译:
一种通用流水线蜂窝阵列的高性能设计
在这封信中,我们提出了一种通用管道元胞阵列(GPCA)的高性能量子点元胞自动机(QCA)设计。GPCA 仅使用一个算术单元即可执行所有基本算术运算。由于其灵活性,高性能 GPCA 设计在大规模 QCA 设计中备受关注。我们使用混合逻辑网络提出了 GPCA 的算术单元和控制单元设计,该网络由三多数 (MAJ)、反相器 (NOT) 和三输入异或 (XOR) 表示$_3$ 3 )。异或的介绍$_3$ 3 操作可以显着减少门、电平和交叉线的数量,从而减少 QCA 布局的面积和时钟周期。实验表明,我们可以同时实现面积和延迟的改进$n$ n -bit (n = 3,4,5) GPCA 设计与最先进的技术相比。
更新日期:2020-01-01
中文翻译:
一种通用流水线蜂窝阵列的高性能设计
在这封信中,我们提出了一种通用管道元胞阵列(GPCA)的高性能量子点元胞自动机(QCA)设计。GPCA 仅使用一个算术单元即可执行所有基本算术运算。由于其灵活性,高性能 GPCA 设计在大规模 QCA 设计中备受关注。我们使用混合逻辑网络提出了 GPCA 的算术单元和控制单元设计,该网络由三多数 (MAJ)、反相器 (NOT) 和三输入异或 (XOR) 表示