Real‐time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most time‐consuming steps of the filtering operation. Log‐based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log‐based hardware multipliers by appropriately altering the filter weights and without increasing the required resources.

中文翻译：

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用于滤波应用的对数乘法中减少错误的有效电路

实时数字信号和图像处理应用（例如滤波）要求高性能。通常，乘法是过滤操作中最耗时的步骤之一。基于对数的乘法器已被用来提高乘法效率，但以准确性为代价。拟议工作的目的是通过适当改变滤波器权重而不增加所需资源来提高基于对数的硬件乘法器的精度。