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An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,
International Journal of Circuit Theory and Applications ( IF 2.3 ) Pub Date : 2020-03-01 , DOI: 10.1002/cta.2759
Thirumalesu Kudithi 1 , Sakthivel R 1
Affiliation  

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, urn:x-wiley:cta:media:cta2759:cta2759-math-0003. This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field urn:x-wiley:cta:media:cta2759:cta2759-math-0004 and urn:x-wiley:cta:media:cta2759:cta2759-math-0005, respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.

中文翻译:

椭圆曲线密码处理器在素数场上的高效硬件实现,

椭圆曲线密码术(ECC)方案的密钥大小,硬件资源以及比Rivest-Shamir-Adleman(RSA)更高的每比特安全性,被广泛用于数字签名应用程序。在这项工作中,我们针对素数场上的雅可比坐标中的椭圆曲线标量乘法(ECSM)提出了一种新的硬件架构,:x-wiley:cta:media:cta2759:cta2759-math-0003。这是点加倍和点加法架构的组合,使用资源共享概念实现以实现高速和低硬件资源,并在现场可编程门阵列(FPGA)和专用集成电路(ASIC)中进行综合。提议的ECSM在Virtex-7 FPGA平台上分别在224位和256位素数字段上花费1.76和2.44 ms。同样,ASIC(GF 40 nm互补金属氧化物半导体[CMOS])技术的实施提供了高能效,在主场ur:x-wiley:cta:media:cta2759:cta2759-math-0004和上的延迟分别为0.46和0.6 ms ur:x-wiley:cta:media:cta2759:cta2759-math-0005。与其他设计相比,该设计在FPGA和ASIC中均提供了更好的面积延迟产品和较高的吞吐量值。
更新日期:2020-03-01
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