We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

我们提出了一种电路级技术，该技术设计了较低的写功率以及抗变异性的9-MOFTET静态随机存取存储单元。由于活动因子的减少以及写操作期间交叉耦合反相器之间的反馈路径的中断，我们提出的位单元具有较低的写功耗。与标准的6T SRAM单元@最小面积相比，它具有更高的读取静态噪声容限（3.09×）。与等面积（最小面积）的8T（S6T）相比，LP9T的写入操作静态余量更高（41％）。这些改进是由于在将位写到存储节点的过程中反馈路径中断而实现的。本文详细研究了过程相关参数变化的影响，环境参数，例如位单元的大多数重要设计参数上的电源电压和温度，并将获得的仿真结果与传统的6-MOSFET（6T）和8-MOSFET（8T）位单元进行比较。它通过显示1.5倍的读取时间变异性更紧密的分散来证明其不变性，与S6T @最小区域相比，读取时间的成本高1.41倍。与8T @ iso-area区域相比，它在读取时间可变性上的分散度也缩小了39％。与标准的8T SRAM单元@ iso区域相比，在写模式期间翻转存储的数据时，它从电源电压汲取了较低的功率（2.06×）。它还将LP9T的关键设计指标与文献中发现的其他少数9T SRAM单元的指标进行了比较。这项工作还实现了使用CNFET的建议设计。