当前位置: X-MOL 学术J. Comput. Electron. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors
Journal of Computational Electronics ( IF 2.1 ) Pub Date : 2020-04-25 , DOI: 10.1007/s10825-020-01502-9
V. Jegadheesan , K. Sivasankaran

For continued scaling with silicon, the stacked nanosheet field-effect transistor (SNSH-FET) is considered to be a major candidate for sub-7-nm technology. The radiofrequency (RF)/analog performance of a three-channel SNSH-FET is studied herein and benchmarked against a fin-shaped field-effect transistor (FinFET) at 7-nm technology and having the same footprint on the wafer. In the existing SNSH-FET on a bulk substrate, the source/drain junction formed on the bulk substrate contributes extra capacitance. An SNSH-FET structure with a source/drain-on-insulator (SDOI) configuration is presented herein, incorporating an extra channel (channel 4) on the bulk. Channel 4 has a supersteep retrograde (SSR) doping profile, which is achieved by placing a 10-nm-thick lightly doped silicon layer (SSR buffer layer) on the ground plane or a punchthrough-stopper (PTS) doped Si substrate. The parasitic source/drain junction capacitance and leakage under channel 4 are alleviated by growing a 10-nm-thick insulator layer before the in situ doped source/drain epiregion (a configuration referred to as SDOI). The presented structure has the same capacitance as the existing three-channel SNSH-FET on a PTS-Si substrate but with a 6% enhanced drive current, thereby achieving an improvement in terms of the delay and RF/analog performance.

中文翻译:

一种源极/绝缘体上的漏极结构,用于提高堆叠的纳米片场效应晶体管的性能

为了继续进行硅缩放,堆叠纳米片场效应晶体管(SNSH-FET)被认为是7纳米以下技术的主要候选者。本文研究了三通道SNSH-FET的射频(RF)/模拟性能,并以7纳米技术的鳍形场效应晶体管(FinFET)为基准,并在晶圆上具有相同的占位面积。在块状衬底上的现有SNSH-FET中,在块状衬底上形成的源极/漏极结贡献了额外的电容。本文介绍了具有绝缘体上源极/漏极(SDOI)配置的SNSH-FET结构,该结构在主体上合并了一个额外的通道(通道4)。通道4具有超陡逆行(SSR)掺杂曲线,这是通过在接地面上放置10纳米厚的轻掺杂硅层(SSR缓冲层)或掺杂有穿通阻挡层(PTS)的Si基板来实现的。通过在原位掺杂的源极/漏极外延区(一种称为SDOI的结构)之前生长10nm厚的绝缘层,可以缓解沟道4下的寄生源极/漏极结电容和泄漏。提出的结构具有与PTS-Si衬底上现有的三通道SNSH-FET相同的电容,但驱动电流提高了6%,从而在延迟和RF /模拟性能方面实现了改善。
更新日期:2020-04-25
down
wechat
bug