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Temperature Sensitivity Analysis of Inner-Gate Engineered JL-SiNT-FET: An Analog/RF Prospective
Cryogenics ( IF 2.1 ) Pub Date : 2020-06-01 , DOI: 10.1016/j.cryogenics.2020.103087
Shubham Tayal , Vikas Mittal , Sunil Jadav , Shikhar Gupta , Ashutosh Nandi , Bal Krishan

Abstract This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (AV) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = FT=100 - FT=400, where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations.

中文翻译:

内栅极工程 JL-SiNT-FET 的温度敏感性分析:模拟/射频前景

摘要 本文探讨了内栅工程无结硅纳米管场效应晶体管 (JL-SiNT-FET) 对模拟/射频性能的温度敏感性。发现工作温度从 400 K 降低到 100 K 改善了所有三种配置(DS-JL-SiNT-FET、D-JL-SiNT-FET、和 S-JL-SiNT-FET) 的 JL-SiNT-FET 相当大。发现 DS-JL-SiNT-FET、D-JL-SiNT-FET 和 S-JL-SiNT-FET 的固有直流增益 (AV) 分别提高了 ~1.8 dB、2.2 dB 和 1.6 dB工作温度从 400 K 降低到 100 K。此外,截止频率 (fT)、最大振荡频率 (fMAX) 的改进,在 JLSiNT-FET 的所有三种配置中,由温度变化引起的增益频率积 (GFP) 和增益频率积 (GFP) 都相应地显着。还观察到由温度降低引起的改进(ΔF = FT=100 - FT=400,其中 F 是模拟/RF FOM)在所有配置中几乎相似。
更新日期:2020-06-01
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