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Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective
Cryogenics ( IF 1.818 ) Pub Date : 2020-04-29 , DOI: 10.1016/j.cryogenics.2020.103087
Shubham Tayal; Vikas Mittal; Sunil Jadav; Shikhar Gupta; Ashutosh Nandi; Bal Krishan

This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (AV) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = FT=100 - FT=400, where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations.
更新日期:2020-04-29

 

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