In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters “stay together” through final implementation. We propose the use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 2× faster than use of hMetis for our largest testcases). Finally, we propose a flow with fast “blob placement” of clusters. The “blob placement” is used as a seed for a global placement tool that performs placement of the flat netlist. With this flow we achieve 20% speedup on the placement of a netlist with 4.9 M instances with less than 3% difference in routed wirelength.

在先进技术节点中，IC实施面临越来越高的设计复杂性以及越来越严格的设计进度要求。因此，需要新的分解方法以及新的预测方法，以帮助降低问题的复杂性有助于避免物理实施流程中的瓶颈和循环的方法。值得注意的是，采用现代设计方法，更好地预测门级网表的最终位置将非常有价值：这将能够在设计SOC布局规划/ RTL计划阶段对性能，拥塞和布局规划的可行性进行更准确的早期评估。在这项工作中，我们研究了应对VLSI网表集群的经典挑战的新标准：网表集群在最终实施过程中如何“保持在一起”。我们建议使用此标准的多个评估器。我们还探讨了模块化的使用驱动的聚类，以识别给定图中的自然聚类，而无需调整VLSI CAD分区方法通常需要的参数和大小平衡约束。我们发现网表超图到图的映射会显着影响结果的质量，并且我们通过实验确定了加权的有效方法，该方法还包括与I / O的拓扑接近性。此外，我们凭经验证明，与传统的VLSI CAD方法相比，基于模块的集群与实际网表位置的关联性更好（我们的方法也比使用hMetis快2倍用于我们最大的测试用例）。最后，我们提出了具有快速“斑点放置”群集的流程。“斑点放置”用作全局放置工具的种子，该工具执行平面网表的放置。通过此流程，我们可以在放置490万个实例的网表时实现20％的加速，而布线距离的差异小于3％。