New schematic for comparator‐based switched‐capacitor (CBSC) integrator is proposed. In comparison with conventional CBSC integrators, the presented circuit helps to reduce significantly the power consumption while improving the signal‐to‐noise ratio (SNR) and the defined figure of merit (FOM). This was obtained by using a second‐generation current conveyor (CCII) in charge scheme. The integrator design is based on the 0.18‐μm CMOS technology with a frequency of 5 MHz; the proposed first‐order CBSC integrator exhibits 22.87 dB as SNR and 60 μW as power dissipation at 1.8‐V supply voltage.

中文翻译：

---

使用电流传送器的增强型基于比较器的开关电容器积分器

提出了基于比较器的开关电容（CBSC）积分器的新原理图。与传统的CBSC积分器相比，该电路有助于显着降低功耗，同时改善信噪比（SNR）和定义的品质因数（FOM）。这是通过在充电方案中使用第二代电流传送器（CCII）获得的。积分器设计基于0.18 µm CMOS技术，频率为5 MHz；建议的一阶CBSC积分器在1.8V电源电压下的SNR为22.87 dB，功耗为60μW。