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A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs
International Journal of Parallel Programming ( IF 1.5 ) Pub Date : 2020-03-05 , DOI: 10.1007/s10766-020-00656-0
Kim Grüttner , Philipp A. Hartmann , Tiemo Fandrey , Kai Hylla , Daniel Lorenz , Stefan Hauck-Stattelmann , Björn Sander , Oliver Bringmann , Wolfgang Nebel , Wolfgang Rosenstiel

Consideration of an embedded system’s timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. In virtual platform, previously only used for functional software verification, our proposed timed value streams enable a hierarchical and composable power model. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platform. Power and timing models can either be generated from a functional C/C++ description or include state-machine based power models to existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports the run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates timing and power back-annotation and power state machine based approaches with timed value streams in two use-cases: An MP3 decoder, compared to a power-aware ISS and gate-level simulation, and an FPGA based many-core architecture against measurements. Finally, the simulation time overhead of the proposed stream based power model is analyzed and discussed.

中文翻译:

用于异构 MPSoC 的基于时间值流的 ESL 时序和功耗估计和仿真框架

在系统级考虑嵌入式系统的时序行为和功耗是一项艰巨的任务。现有复杂的工具和技术可用于评估单个组件(例如定制硬件和软件以及 IP 组件)的功率和时序。在本文中,我们展示了一个 ESL 框架,用于对由软件、定制硬件和第 3 方 IP 组件组成的异构 MPSoC 进行时序和功耗感知虚拟系统原型设计。在以前仅用于功能软件验证的虚拟平台中,我们提出的定时价值流支持分层和可组合的电源模型。我们提议的 ESL 框架支持将广泛的系统级时序和功耗模型集成到虚拟平台中。电源和时序模型可以从功能 C/C++ 描述生成,也可以将基于状态机的电源模型包含到现有的功能和定时虚拟平台(黑盒)组件中。我们基于定时价值流的电源模型支持不同平台电源管理策略的运行时分析,具有可配置的时间抽象,支持仿真速度和精度权衡。这项工作在两个用例中使用定时值流评估基于时序和功率反向注释和功率状态机的方法:MP3 解码器,与功率感知 ISS 和门级仿真相比,以及基于 FPGA 的众核架构反对测量。最后,分析和讨论了所提出的基于流的功率模型的仿真时间开销。
更新日期:2020-03-05
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