Modular division operation has important application in public-key cryptosystems. It is the most complex and time-consumed operation in RSA and ECC. Its secure and efficient implementation greatly affects the secure and performance of these cryptosystems. In this paper, a modular division algorithm embedding with error detection is proposed. Four computing types of ASIC implementation architectures (Type-8, Type-16, Type-32, Type-64) are explored to seek the optimal tradeoff among error detection ratio, time overhead and hardware overhead. These implementation architectures are modeled in Verilog language and synthesized using Synopsys Design Compiler with OSU 90 nm CMOS standard cell library. Experiment results show that the proposed Type-64 can get almost 100% error detection probability with an average of 24.71% extra area overhead and 0.52% time overhead. In addition, for the implementation of single modular division module, the proposed Type-64 architecture saves 60.74% area overhead on average with a slight decrease of throughput rate compared with the state-of-the-art re- search. This implementation not only greatly reduces the area overhead of modular division but also improves the security of modular division implementation.

模块化除法运算在公钥密码系统中具有重要的应用。这是RSA和ECC中最复杂且耗时的操作。它的安全和有效实现极大地影响了这些密码系统的安全性和性能。本文提出了一种嵌入了错误检测的模块化划分算法。探索了四种计算类型的ASIC实现架构（类型-8，类型-16，类型-32，类型-64），以在错误检测率，时间开销和硬件开销之间寻求最佳平衡。这些实现架构以Verilog语言建模，并使用Synopsys Design Compiler和OSU 90  nm进行了综合CMOS标准单元库。实验结果表明，提出的Type -64可以得到几乎100％的错误检测概率，平均为24 。71％的额外区域开销和0 。52％的时间开销。此外，对于实施单个模块化划分模块，建议的Type -64体系结构可节省60 。与最新技术相比，平均面积开销为74％，吞吐率略有下降。这种实现方式不仅大大减少了模块化划分的面积开销，而且提高了模块化划分实现的安全性。