Settling time is an important performance metric in digital-to-analog converters (DACs) that are used for dynamic calibration applications. To obtain an area efficient DAC design, periodic sequences are generated from sigma-delta modulators (ΣΔMs) using software, stores the sequence in memory and then passes it to a low-pass filter (LPF). In this brief, the sigma-delta (ΣΔ) bitstream generated in software will be optimized such that it yields a system that settles faster and is more area efficient. Two optimization routines are used, namely, serial method and random method algorithms. The random method is chosen to optimize the ΣΔ bitstreams for its computational simplicity. It will be shown, that using the random method routine provides at least 46% improvement in settling time performance of a 12-bit DAC, used in the paper as a design example. Moreover, it offers silicon area savings by at least 10% for resistor components and 35% for capacitor components. Similar results were obtained for 8 to 11 bits of resolution.

中文翻译：

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动态校准应用中用于直流信号生成的优化周期ΣΔ位流

建立时间是用于动态校准应用的数模转换器（DAC）的重要性能指标。为了获得面积有效的DAC设计，使用软件从sigma-delta调制器（ΣΔMs）生成周期序列，并将该序列存储在内存中，然后将其传递到低通滤波器（LPF）。在本简介中，将对软件中生成的sigma-delta（ΣΔ）比特流进行优化，以使其产生一个沉降速度更快，区域效率更高的系统。使用了两种优化例程，即串行方法和随机方法算法。选择随机方法来优化ΣΔ位流，以简化计算。将显示，使用随机方法例程可将12位DAC的建立时间性能至少提高46％，在本文中用作设计示例。此外，它为电阻器组件节省了至少10％的硅面积，为电容器组件节省了35％的硅面积。对于8到11位的分辨率，获得了相似的结果。