Newest technologies of integrated circuits manufacture require a communication architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple Cell Upsets (MCU). Besides, as the technology scales down, the probability of MCU increases. Thus, applying an Error Correction Code (ECC) in NoC buffers may come as a solution for reliability issues, although increasing the design costs and requiring a buffer with higher storage capacity. This work evaluates two models of data arrangement for NoC buffers protected by three types of ECCs, preserving the protection of the storage information, and reducing the area usage and power dissipation compared to other solutions. We evaluated the performance of fault-tolerant NoC buffer schemes by applying the models on three types of ECC and measuring the buffer area, power overhead and error coverage. The experimental results show that the use of the Optimized model keeps the reliability for MCU while reducing area consumption and power dissipation in approximately 25% and 30%, respectively.

集成电路制造的最新技术需要通信架构，例如片上网络（NoC）。NoC缓冲区易受多单元翻转（MCU）的影响。此外，随着技术的缩减，MCU的可能性也随之增加。因此，尽管增加了设计成本并需要具有更高存储容量的缓冲区，但在NoC缓冲区中应用纠错码（ECC）可能会解决可靠性问题。这项工作评估了由三种类型的ECC保护的NoC缓冲区的两种数据排列模型，与其他解决方案相比，保留了对存储信息的保护，并减少了面积使用和功耗。通过将模型应用于三种类型的ECC并测量缓冲区面积，我们评估了容错NoC缓冲区方案的性能，电源开销和错误覆盖率。实验结果表明，使用优化模型可以保持MCU的可靠性，同时将面积消耗和功耗分别降低约25％和30％。