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Investigation on junctionless floating body DRAMs including Trap Assisted Tunneling
Solid-State Electronics ( IF 1.7 ) Pub Date : 2020-04-01 , DOI: 10.1016/j.sse.2020.107799
Gino Giusi

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed in detail the physics of operation and the performances of FB-DRAM cells based on JL transistors including the effect of Trap-Assisted-Tunneling (TAT), neglected in most of previous works. As expected, TAT severely limits the retention time due to the large doping, in particular during HOLD operation. The discussion is supported by 2D device simulation on a double gate junctionless transistor including the effect of statistical variability induced by random dopant fluctuations, and the technology (bandgap, lifetime) scaling. It is found that the cell, at least at the nanoscale, can work only by independent gate operation, having maximum performance when the bottom gate works at the limit of the BBT bias region during READ, and that at a gate length as large as 100 nm and fin width of 10 nm the cell can sustain the high doping induced variability to a retention time in the order of 1 ms, while the use of materials with higher bandgap (~1.3 eV) than Silicon can improve the retention time to the order of 10 ms. However several concerns remain on their actual use related to the necessary bias level and to the impact of the actual technologies on the lifetime, which strongly affects TAT degradation.



中文翻译:

陷阱辅助隧穿的无结浮体DRAM研究

无结晶体管(JL)和单晶体管(1T)DRAM的出现是为了分别提高逻辑和易失性存储器的可伸缩性。在最近的一些论文中,浮体(FB)DRAM(一类1T-DRAM)和JL晶体管已被结合起来,以提出一种解决方案来克服常规1T-1C DRAM单元的尺寸限制。在本文中,他们详细讨论了基于JL晶体管的FB-DRAM单元的工作物理原理和性能,包括在以前的大多数工作中都忽略的陷阱辅助隧穿(TAT)效应。正如预期的那样,TAT由于掺杂量大而严重限制了保留时间,尤其是在HOLD操作期间。讨论由双栅无结晶体管上的2D器件仿真支持,包括随机掺杂物波动引起的统计变化和技术(带隙,寿命)缩放的影响。已经发现,至少在纳米级,该单元只能通过独立的栅极操作来工作,当底栅极在读取期间处于BBT偏置区域的极限时以及栅极长度高达100时,才具有最佳性能。纳米和鳍片宽度为10 nm时,该单元可以维持高掺杂诱导的可变性,使保留时间达到1 ms左右,而使用具有比硅更高的带隙(〜1.3 eV)的材料可以将保留时间提高到大约10毫秒。

更新日期:2020-04-01
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