Solid-State Electronics ( IF 1.7 ) Pub Date : 2019-11-26 , DOI: 10.1016/j.sse.2019.107731 F. Tcheme Wakam , J. Lacord , M. Bawedin , S. Martinie , S. Cristoloveanu , G. Ghibaudo , J.-Ch. Barbe
In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge threshold voltage. The complete A2RAM compact model is implemented in Verilog-A to allow the use of SPICE simulator. DC and memory characteristics are validated by TCAD. SPICE simulations show the operation of 2 × 2 A2RAM matrix.
中文翻译:
A2RAM紧凑建模:从DC到1T-DRAM存储器操作
在这项工作中,我们提出了无电容器A2RAM存储单元的紧凑模型。它是通过将A2RAM DC紧凑模型与模拟存储器状态的等效电路相结合而获得的。通过将A2RAM体系结构视为SOI晶体管与可变电阻桥并联的组合来实现DC建模。至关重要的方面是对电桥阈值电压的分析描述。完整的A2RAM紧凑模型在Verilog-A中实现,以允许使用SPICE模拟器。DC和存储器特性已通过TCAD验证。SPICE仿真显示了2×2 A2RAM矩阵的操作。