This paper analyses and rectifies the shortcomings of reversible contrast mapping (RCM) algorithm for invisible watermarking. The proposed corrected RCM algorithm is tested by taking a gray scaled video input. The quality of services and structural similarity index matrix (SSIM) of each frame of the input video are tested in software environment. The video is obtained by OV7670 camera through Zed-board in fully field programmable gate array (FPGA) based hardware environment. FPGA devices based corrected high level synthesis of the proposed algorithm is presented. The suggested system engages pipeline structure and practices parallelism to achieve high performance. The quality of services and SSIM are also tested using FPGA devices and the comparative results with software implementations are explained. To process thirty (640 × 480) image blocks with 150 MHz clock we obtain a latency of 876.626 ns with throughput 62.328 Mbps. The critical path for single cycle is 5.992 ns. The number of resources essential is similar for watermark decoding with an improved schedule. The results acquired after implementation on Xilinx Virtex 7-XC7V2000T and programmable system-on-chip (Zynq - XC7Z030) FPGA devices confirm the practicability of real-time use with low cost and great speed.

本文分析并纠正了可逆对比度映射（RCM）算法在不可见水印中的缺点。通过采用灰度视频输入来测试提出的校正后的RCM算法。在软件环境中测试了输入视频每一帧的服务质量和结构相似性指标矩阵（SSIM）。该视频由OV7670摄像机通过Zed-board在基于全现场可编程门阵列（FPGA）的硬件环境中获得。提出了基于FPGA器件的修正高级综合校正算法。建议的系统采用管道结构并实践并行性以实现高性能。还使用FPGA器件测试了服务质量和SSIM，并说明了与软件实现的比较结果。为了以150 MHz时钟处理三十个（640×480）图像块，我们获得了876.626 ns的延迟和62.328 Mbps的吞吐量。单周期的关键路径为5.992 ns。对于具有改进的调度的水印解码来说，必不可少的资源数量是相似的。在Xilinx Virtex 7-XC7V2000T和可编程片上系统（Zynq-XC7Z030）FPGA器件上实施后获得的结果证实了低成本，高速度实时使用的实用性。