This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I_on more than double, while the off-state currents I_off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I_on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.

本文介绍了一种高效的三进制闪存ADC，其在45 nm技术节点上使用创新的栅极重叠隧道FET（GOTFET）设计。所提出的GOTFET的导通电流I _on大于两倍，而截止状态电流I _off至少比相同宽度的标准45 nm CMOS技术的相应值低一个数量级。用建议的GOTFET代替MOSFET可显着降低静态功耗并提高性能。然而，较高的我_上也增加了动态功率。为了使动态功耗最小，我们提出了一种基于互补GOTFET（CGOT）的新型比较器设计。除了GOTFET技术的固有优势外，所提出的设计还降低了动态功率，因此最终功率延迟乘积（PDP）仅是传统CMOS比较器设计中PDP的6.3％。除了与创新的GOTFET器件有关的新颖性之外，这项工作还报告了至少两倍的电路级新颖性。首先，我们提出了一种新颖的基于CGOT的比较器电路设计，该设计除了具有GOTFET的优点之外，还进一步降低了动态功耗，使得PDP小于设计有GOTFET的传统比较器的原始PDP的1/3。其次，提出的基于CGOT的ADC只需48个晶体管即可将比较器输出编码为2位三进制输出，这比文献中先前报道的基于2位CMOS三元闪存ADC设计所需的70个晶体管低30％。我们提出了一种高效的2位三进制闪存ADC，其分辨率为50 mV，输入量化为9个电平。随后，我们以使用标准45 nm CMOS技术库实现的相同ADC电路为基准，对提出的CGOT三元闪存ADC的性能进行了基准测试，所有相应的器件均具有相同的宽度。我们证明，除了比相应的CMOS ADC优越的性能外，提出的CGOT ADC设计还消耗了显着较低的功耗。提出的CGOT ADC的整体PDP仅为相应CMOS设计中PDP的6.3％。