Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Non-compatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS′89 benchmarks circuits reflect its effectiveness in achieving better compression.

由于集成电路片上复杂性的提高，测试数据已大大增加。这进一步增加了测试数据的传输时间和测试仪的内存。不相关的测试位会增加测试功率。本文提出了一种基于两阶段块合并的测试数据最小化方案，该方案减少了测试位，测试时间和测试功率。将测试数据划分为固定大小的块，然后使用两阶段编码技术对其进行压缩。在第一阶段，将连续的块合并以保留代表块。在第二阶段中，基于通过将保留的图案块分成两半而形成的子块之间存在十个不同的子情况，对保留的图案块进行进一步编码。非兼容块也分为两个子块，并尝试使用较少的位进行编码。提出了检索原始测试数据的解压缩架构。对应于不同的ISCAS'89基准电路获得的仿真结果反映了其在实现更好压缩方面的有效性。