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Evaluating nanomagnetic logic circuit layouts using different clock schemes
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2020-04-22 , DOI: 10.1007/s10470-020-01648-3
Ruan Evangelista Formigoni , Leandro Lázaro Araújo Vieira , Omar Paranaiba Vilela Neto , Ricardo Ferreira , José Augusto M. Nacif

The complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors’ feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of field-coupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS transistor due to the complete absence of static energy dissipation. When designing nanomagnetic circuitry, several challenges arise, such as the design of a clocking system able to avoid signal disruption due to the thermal noise effect. In this paper, we compare four NML clocking schemes: BANCS, USE, RES, and 2DDWave by analyzing scalability and area overhead of combinational and sequential circuits.



中文翻译:

使用不同的时钟方案评估纳米磁逻辑电路布局

随着晶体管特征尺寸的减小,互补金属氧化物半导体技术CMOS已达到其物理极限。一种有希望的替代方法是纳米磁逻辑技术(NML),这是场耦合纳米计算的范例。由于完全没有静态能量耗散,该技术应用单域纳米磁铁来实现数字逻辑,其开关能量比CMOS晶体管低几个数量级。当设计纳米磁性电路时,出现了一些挑战,例如设计时钟系统,能够避免由于热噪声效应而引起的信号中断。在本文中,我们通过分析组合电路和时序电路的可扩展性和面积开销,比较了四种NML时钟方案:BANCS,USE,RES和2DDWave。

更新日期:2020-04-23
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