This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces of its reconfigurable modules, the structure of the communications, the inclusion of specialized modules to handle and optimize circuit reconfiguration at runtime, and the organization of the reconfigurable partitions. We evaluate two methods to select the new target partition for modules in faulty partitions and design their hardware as intellectual property modules. We evaluate the performance and scalability of this approach using a trapezoidal shaper, a filter used to detect high-energy particles in radiation experiments, and we carry out the experiments with a variable number of modules and reconfigurable partitions using the two selection algorithms. The proposal is compared with nonfault-tolerant and triple modular redundancy approaches, and it remains functional with up to $12\times $ more injected faults than those.

中文翻译：

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提高基于总线的可重构设计容错性的最佳运行时算法

本文介绍了一种对动态、部分可重新配置的现场可编程门阵列 (FPGA) 基板中的永久效应提供容错的方法。我们的建议包括在运行时修改 FPGA 配置，以避免永久损坏 FPGA 的区域。它要求电路设计满足关于其可重构模块的功能和接口、通信结构、在运行时处理和优化电路重构的专用模块的包含以及可重构分区的组织的若干要求。我们评估了为故障分区中的模块选择新目标分区的两种方法，并将其硬件设计为知识产权模块。我们使用梯形整形器评估这种方法的性能和可扩展性，用于在辐射实验中检测高能粒子的过滤器，我们使用两种选择算法以可变数量的模块和可重新配置的分区进行实验。该提议与非容错和三重模块化冗余方法进行了比较，它仍然可以正常工作，注入的故障比那些多 12 倍。