This paper proposes a high-throughput median finding architecture where the sorting of an incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work, four clock pulses are required to populate the \(4\times 4\) window as four pixels are read at a time from the incoming grey image. This median finding process is carried out by parallel and pipeline median a rchitecture. The proposed median finding process requires two read operations to take eight input pixels and generates four output pixels with a latency of seven clock cycles. The proposed architecture has been implemented on Xilinx Virtex–VII FPGA. The proposed architecture is synthesized using the SoC Encounter along with Faraday 90 nm standard cell library. The maximum operating frequency is 950.57 MHz, the total gate count is 4540, area is \(0.40543 \hbox { mm}^{2}\) and the dissipated power is 0.92617 mW. The high-throughput, high-speed and low-power-dissipation nature of the proposed architecture make it suitable for computationally extensive Internet of Things (IoT) applications.

本文提出了一种高通量中值发现架构，其中输入像素的排序由高速比较和选择（CS）模块执行。在这项工作中，需要四个时钟脉冲来填充\（4 \ times 4 \）窗口，因为从传入的灰度图像中一次读取四个像素。该中位数查找过程是通过并行和流水线中位数架构来执行的。提出的中值查找过程需要两次读取操作才能占用八个输入像素，并生成四个输出像素，延迟为七个时钟周期。拟议的架构已在Xilinx Virtex-VII FPGA上实现。使用SoC Encounter和法拉第90 nm标准单元库对提出的体系结构进行了综合。最大工作频率为950.57 MHz，总门数为4540，面积为\（0.40543 \ hbox {mm} ^ {2} \）耗散功率为0.92617 mW。所提出的架构的高吞吐量，高速和低功耗特性使其适合于计算范围广泛的物联网（IoT）应用。