This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

中文翻译：

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Cryo-CMOS 失配的表征和建模

本文介绍了在低温下运行的商用 40 纳米体 CMOS 技术的器件匹配研究。针对器件匹配优化的晶体管对和线性阵列在 300 K 至 4.2 K 的温度范围内进行了表征。提取了与失配相关的器件参数，即阈值电压和电流因子，从中可以看出研究了作为温度和器件尺寸函数的绝对值和可变性。结果表明，Pelgrom 标度定律在 4.2 K 时也有效，并且简化的 Croon 模型能够准确预测在整个温度范围内从中度到强反转的漏极电流失配。此外，线性器件阵列的特性表明在极低温度下边缘效应加剧，因此需要在阵列边界添加虚拟器件。这项研究的结果是第一个能够预测大范围工作区域和温度下的失配的模型。