This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feed-through effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage ( $\text{I}_{\mathrm {D}}$ - $\text{V}_{\mathrm {GS}}$ ) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver.

中文翻译：

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用于 AMLCD 的时钟信号延迟较少的 a-Si:H 栅极驱动器的低泄漏电容耦合结构

这项工作提出了一种具有低泄漏电容耦合结构的氢化非晶硅 (a-Si:H) 薄膜晶体管 (TFT) 栅极驱动器，以减少时钟信号的延迟。所提出的电路抑制了由时钟馈通效应引起的驱动TFT栅极节点的波动，减少了从时钟信号线流向具有低电压电平的电源线的漏电流。这种漏电流的减少可以改善时钟信号电压的劣化，从而避免扫描脉冲上升时间的增加。用于提取漏极电流与栅源电压的测量值 ( $\text{I}_{\mathrm {D}}$ —— $\text{V}_{\mathrm {GS}}$ ) 制作的 a-Si:H TFT 曲线，通过拟合获得的曲线来建立模拟 TFT 模型。对于相同参数的 TFT 和电容，所提出电路的漏电流和输出波形的上升时间分别比先前开发的栅极驱动器低 45.45% 和 21.36%。